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19-3155; Rev 0; 5/04
KIT ATION EVALU ILABLE AVA
Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP
General Description
The MAX8543/MAX8544 current-mode, constant-frequency PWM buck controllers operate from a 3V to 13.2V input supply and generate adjustable 0.8V to 0.9 x VIN output voltages at loads up to 25A. They feature adjustable switching frequency and synchronization for noise-sensitive applications. The MAX8543/MAX8544 can start with (or without) a preexisting bias on the output, without discharging the output. This feature simplifies tracking supply designs for core and I/O applications and redundant supply designs. The MAX8543/MAX8544 use the DC resistance of the output inductor as the current-sense element for lossless, low-cost current sensing. The current-sense threshold can be set to four discrete levels to accommodate inductors with different DC resistance values. The MAX8544 features a power-OK monitor and two MAX8544 controllers that can operate at 180 out-ofphase for dual-output applications. Prebias Startup/Monotonic 1% Output Accuracy Ceramic, Polymer, or Electrolytic Capacitors 200kHz to 1MHz Adjustable Frequency 160kHz to 1.2MHz Synchronization Lossless, Foldback Current Limit Overvoltage Protection Enable (On/Off) Adjustable Soft-Start MAX8544 Latch-Off/Autorecovery Power-OK Monitor Out-of-Phase Clock Output
Features
MAX8543/MAX8544
Applications
Base Stations Networks and Telecom Storage Servers
PART MAX8543EEE MAX8544EEP
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 QSOP 20 QSOP
Pin Configurations appear at end of data sheet.
Typical Operating Circuit
INPUT 3V TO 13.2V VIN = 3V TO 5.5V VL
ON OFF EN FSYNC OPTIONAL SYNCHRONIZATION SS
IN
BST DH LX OUTPUT 0.8V TO 0.9 x VIN UP TO 25A
MAX8543
COMP ILIM GND PGND
DL
CS+
CSPOK (MAX8544) FB
________________________________________________________________ Maxim Integrated Products
1
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
ABSOLUTE MAXIMUM RATINGS
IN, EN, CS+, CS- to GND .......................................-0.3V to +14V BST, DH to LX ..........................................................-0.3V to +6V BST to GND ............................................................-0.3V to +20V DL, COMP, ILIM2, SS, SYNCO, FSYNC to GND .......................................-0.3V to (VVL + 0.3V) VL, FB, POK, ILIM1, ILIM, MODE to GND ................-0.3V to +6V PGND to GND .......................................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.3mW/C above +70C) .......666.7mW 20-Pin QSOP (derate 9.1mW/C above +70C) .......727.3mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 13.2V, VBST - VLX = 5V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Operating Input Voltage Range Quiescent Supply Current Shutdown Supply Current VL Undervoltage-Lockout Trip Level Output Voltage Adjust Range (VOUT) VL Output Voltage VL Output Current VOLTAGE REFERENCE SS Shutdown Resistance SS Soft-Start Current Soft-Start Ramp Time ERROR AMPLIFIER FB Regulation Voltage Transconductance COMP Shutdown Resistance FB Input Leakage Current FB Input Common-Mode Range CURRENT-SENSE AMPLIFIER VILIM1 = 0V Voltage Gain VOUT = 0 to 13V VILIM1 = (1/3)VVL VILIM1 = (2/3)VVL VILIM1 = VVL CURRENT LIMIT ILIM2 Output Current (MAX8544 Only) ILIM1 Input Current RILIM2 = 50k to 200k VILIM1 = 0V or VVL 4.5 -1 5 5.5 +1 A A 8.8 4.8 3.2 2.4 11 6 4 3 13.2 7.2 4.8 3.6 V/V From COMP to GND, VEN = 0V VFB = 0.9V -0.1 0.792 70 0.8 110 20 5 0.808 160 100 100 +0.9 V S nA V From SS to GND, VEN = 0V VREF = 0.625V Output from 0% to 100%, CREF = 0.01F to 1F 14 20 24 33 100 34 A ms/F CONDITIONS VL connected to IN for VIN < 5.5V VFB = 0.9V, no switching EN = GND, MODE = GND, IN not connected to VL EN = GND, VL = IN, MODE = GND VVL rising, typical hysteresis is 80mV (Note 1) 5.5V < VIN < 13.2V, 1mA < IVL < 75mA 2.52 0.8 4.5 5 5.5 75 2.7 MIN 3.0 2 TYP MAX 13.2 3 10 20 2.88 UNITS V mA A V V V mA
2
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 13.2V, VBST - VLX = 5V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER CONDITIONS VCS+ - VCS-, VILIM1 = 0V VCS+ - VCS-, VILIM1 = (1/3)VVL VCS+ - VCS-, VILIM1 = (2/3)VVL Current-Limit Threshold VCS+ - VCS-, VILIM1 = VVL VLX - VPGND, RILIM2 = 50k (MAX8544 only) VLX - VPGND, RILIM2 = 200k (MAX8544 only) VLX - VPGND, VFB = 0.8V (MAX8543 only) VLX - VPGND, VFB = 0V (MAX8543 only) Negative Current-Limit Threshold CS+, CS- Input Current CS+, CS- Input Common-Mode Range OSCILLATOR Switching Frequency Minimum Off-Time Minimum On-Time FSYNC Synchronization Range FSYNC Input High Pulse Width FSYNC Input Low Pulse Width FSYNC Rise/Fall Time SYNCO Phase Shift from DH Rising SYNCO Output Low Level SYNCO Output High Level MOSFET DRIVERS DH On-Resistance, High State DH On-Resistance, Low State DL On-Resistance, High State DL On-Resistance, Low State Break-Before-Make Dead Time LX, BST, IN Leakage Current THERMAL PROTECTION Thermal Shutdown Thermal-Shutdown Hysteresis Rising temperature +160 15 C C (VBST - VLX) = 5V (VBST - VLX) = 3V (VBST - VLX) = 5V (VBST - VLX) = 3V VVL = 5V VVL = 3V VVL = 5V VVL = 3V Low-side off to high-side on High-side off to low-side on VBST = 18.7V, VLX = 13.2V, VIN = 13.2V 1 1.2 1 1.2 1 1.2 0.6 0.8 55 40 5 1.7 2.5 2.5 2.5 ns A RFSYNC = 18.2k, free-running mode, at maximum duty cycle ISYNCO = 5mA ISYNCO = 5mA VVL - 1V 165 180 RFSYNC = 18.2k RFSYNC = 158k Measured at DH Measured at DH 160 100 100 100 195 0.4 150 800 1000 200 220 90 270 145 1200 1200 kHz ns ns kHz ns ns ns Degrees V V % of positive-direction current limit VLX - VPGND VCS+ = VCS- = 0 or 5V MIN 38.5 85 127.5 170 -42.5 -160 -110 -20 -25 -40 0 TYP 50 100 150 200 -50 -200 -130 -30 -50 MAX 56.5 115 172.5 230 -57.5 -240 -150 -40 -85 +40 13.2 % A V mV UNITS
MAX8543/MAX8544
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 13.2V, VBST - VLX = 5V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER POK Power-OK Threshold POK Output Voltage, Low POK Leakage Current, High OVERVOLTAGE PROTECTION (OVP) Output Overvoltage Fault-Trip level MODE CONTROL MODE Logic-Level Low MODE Logic-Level High MODE Input Current SHUTDOWN CONTROL EN Logic-Level Low EN Logic-Level High EN Input Current 3V VVL 5.5V 3V VVL 5.5V VEN = 0 or 5.5V VEN = 13.2V 2 -1 1.5 +4 6 0.45 V V A 3V VVL 5.5V 3V VVL 5.5V VMODE = 0V MODE = VL 1.8 -1 5 +1 10 0.4 V V A Rising edge compared to regulation set point; triggers after one or two clock cycles +110 +115 +120 % VFB rising, percent of VOUT, typical hysteresis is 3% VFB = 0.6V, IPOK = 2mA VPOK = 5.5V 88 91 25 0.001 94 200 1 % mV A CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
(VIN = 13.2V, VBST - VLX = 5V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER Operating Input Voltage Range Quiescent Supply Current Shutdown Supply Current VL Undervoltage-Lockout Trip Level Output Voltage Adjust Range (VOUT) VL Output Voltage VL Output Current VOLTAGE REFERENCE SS Shutdown Resistance SS Soft-Start Current ERROR AMPLIFIER FB Regulation Voltage Transconductance COMP Shutdown Resistance FB Input Leakage Current FB Input Common-Mode Range From COMP to GND, VEN = 0V VFB = 0.9V -0.1 0.788 70 0.808 160 100 100 +0.9 V S nA V From SS to GND, VEN = 0V VREF = 0.625V 14 100 34 A CONDITIONS VL connected to IN for VIN < 5.5V VFB = 0.9V, no switching EN = GND, MODE = GND, IN not connected to VL EN = GND, VL = IN, MODE = GND VVL rising, typical hysteresis is 80mV (Note 1) 5.5V < VIN < 13.2V, 1mA < IVL < 75mA 2.52 0.8 4.5 5.5 75 MIN 3.0 MAX 13.2 3 10 20 2.88 UNITS V mA A V V V mA
4
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 13.2V, VBST - VLX = 5V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER CURRENT-SENSE AMPLIFIER VILIM1 = 0V Voltage Gain VOUT = 0 to 13V VILIM1 = (1/3)VVL VILIM1 = (2/3)VVL VILIM1 = VVL CURRENT LIMIT ILIM2 Output Current (MAX8544 Only) ILIM1 Input Current RILIM2 = 50k to 200k VILIM1 = 0V or VVL VCS+ - VCS-, VILIM1 = 0V VCS+ - VCS-, VILIM1 = (1/3)VVL VCS+ - VCS-, VILIM1 = (2/3)VVL Current-Limit Threshold VCS+ - VCS-, VILIM1 = VVL VLX - VPGND, RILIM2 = 50k (MAX8544 only) VLX - VPGND, RILIM2 = 200k (MAX8544 only) VLX - VPGND, VFB = 0.8V (MAX8543 only) VLX - VPGND, VFB = 0V (MAX8543 only) Negative Current-Limit Threshold CS+, CS- Input Current CS+, CS- Input Common-Mode Range OSCILLATOR Switching Frequency Minimum Off-Time Minimum On-Time FSYNC Synchronization Range FSYNC Input High Pulse Width FSYNC Input Low Pulse Width FSYNC Rise/Fall Time SYNCO Phase Shift from DH Rising SYNCO Output Low Level SYNCO Output High Level MOSFET DRIVERS DH On-Resistance, High State DH On-Resistance, Low State DL On-Resistance, High State DL On-Resistance, Low State LX, BST, IN Leakage Current (VBST - VLX) = 5V (VBST - VLX) = 5V VVL = 5V VVL = 5V VBST = 18.7V, VLX = 13.2V, VIN = 13.2V 2.5 2.5 2.5 1.7 5 A RFSYNC = 18.2k ISYNCO = 5mA ISYNCO = 5mA VVL - 1V 165 RFSYNC = 18.2k Measured at DH Measured at DH 160 100 100 100 195 0.4 800 150 1200 270 140 1200 kHz ns ns kHz ns ns ns Degrees V V % of positive-direction current limit VLX - VPGND VCS+ = VCS- = 0V or 5V 4.2 -1 38.5 85 127.5 170 -40 -160 -110 -20 -25 -40 0 5.5 +1 56.5 115 172.5 230 -60 -240 -150 -40 -85 +40 13.2 % A V mV A A 8.8 4.8 3.2 2.4 13.2 7.2 4.8 3.6 V/V CONDITIONS MIN MAX UNITS
MAX8543/MAX8544
5
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 13.2V, VBST - VLX = 5V, TA = -40C to +85C, unless otherwise noted.) (Note 2)
PARAMETER POK Power-OK Threshold POK Output Voltage, Low POK Leakage Current, High OVERVOLTAGE PROTECTION (OVP) Output Overvoltage Fault-Trip level MODE CONTROL MODE Logic-Level Low MODE Logic-Level High MODE Input Current SHUTDOWN CONTROL EN Logic-Level Low EN Logic-Level High EN Input Current 3V VVL 5.5V 3V VVL 5.5V VEN = 0V or 5.5V VEN = 13.2V 2 -1 +4 6 0.45 V V A 3V VVL 5.5V 3V VVL 5.5V VMODE = 0V MODE = VL 1.8 -1 +1 10 0.4 V V A Rising edge compared to regulation set point; triggers after one or two clock cycles +110 +120 % VFB rising, percent of VOUT, typical hysteresis is 3% VFB = 0.6V, IPOK = 2mA VPOK = 5.5V 88 94 200 1 % mV A CONDITIONS MIN MAX UNITS
Note 1: Maximum output voltage is limited by maximum duty cycle and external components. Note 2: Specifications to -40C are guaranteed by design and not production tested.
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT WITH 12V INPUT
MAX8543 toc01
EFFICIENCY vs. LOAD CURRENT WITH 3.3V INPUT
MAX8543 toc02
LOAD REGULATION WITH 12V INPUT
2.54 2.53 OUTPUT VOLTAGE (V) 2.52 2.51 2.50 2.49 2.48 2.47
MAX8543 toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 10 LOAD CURRENT (A) fS = 600kHz VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 1 10 LOAD CURRENT (A) fS = 500kHz VOUT = 1.8V VOUT = 1.5V VOUT = 2.5V
2.55
2.46 2.45 0 3 6 9 12 15 LOAD CURRENT (A)
100
100
LINE REGULATION WITH 12V INPUT AND 2.5V OUTPUT
MAX8543 toc04
LINE REGULATION 3.0V TO 3.6V INPUT
MAX8543 toc05
OSCILLATOR FREQUENCY vs. INPUT VOLTAGE
580 OSCILLATOR FREQUENCY (kHz) 560 540 520 500 480 460 440 420 R6 = 53.6k 3.0 3.5 4.0 4.5 5.0 5.5 TA = +25C TA = -40C TA = +85C
MAX8543 toc06
2.510 2.508 2.506 OUTPUT VOLTAGE (V) 2.504 2.502 2.500 2.498 2.496 2.494 2.492 2.490 10.8 11.4 12.0 INPUT VOLTAGE (V) 12.6 15A LOAD NO LOAD
2.54 2.52 OUTPUT VOLTAGE (V) 2.50 2.48 2.46 2.44 2.42 15A LOAD fS = 350kHz 15A LOAD fS = 500kHz
600
NO LOAD
400 3.0 3.1 3.2 3.3 3.4 3.5 3.6 INPUT VOLTAGE (V) INPUT VOLTAGE (V)
13.2
OSCILLATOR FREQUENCY vs. INPUT VOLTAGE
680 OSCILLATOR FREQUENCY (kHz) 660 640 620 600 580 560 540 520 500 5.5 7.5 9.5 INPUT VOLTAGE (V) 11.5 13.5 TA = -40C TA = +25C TA = +85C
MAX8543 toc07
700
R6 = 42.2k
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAX8544 STEP-LOAD RESPONSE 7.5A TO 15A TO 7.5A (5A/s)
MAX8543 toc08
MAX8544 STEP-LOAD RESPONSE 1.5A TO 15A TO 1.5A (5A/s)
MAX8543 toc09
VOUT
50mV/div AC-COUPLED
VOUT
100mV/div AC-COUPLED
IOUT
5A/div
IOUT
5A/div
0 10s/div 10s/div
0
MAX8544 POWER-UP WAVEFORMS
MAX8543 toc10
MAX8544 POWER-DOWN WAVEFORMS
MAX8543 toc11
VIN VIN VOUT 2V/div VPOK 5V/div VOUT VPOK 2V/div 5V/div
5V/div IL 10A/div 0 2ms/div 2ms/div
2V/div 10A/div 0
IL
MAX8543 POWER-UP WAVEFORMS
MAX8543 toc12
MAX8543 POWER-DOWN WAVEFORMS
MAX8543 toc13
VIN
2V/div
VIN 2V/div
1V/div VOUT VOUT 1V/div
10A/div IL IL 0 2ms/div
10A/div 0
2ms/div
8
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
MAX8544 ENABLE WAVEFORMS
MAX8543 toc14
FSYNC AND SYNCO WAVEFORMS
MAX8543 toc15
VOUT VEN 5V/div VLX VOUT 2V/div VPOK 5V/div VSYNCO IL 2ms/div 10A/div 0 2s/div VFSYNC
1V/div
10V/div
5V/div
5V/div
SHORT CIRCUIT AND RECOVERY
MAX8543 toc16
OVERVOLTAGE PROTECTION WITH 15A LOAD
MAX8543 toc17
VIN VOUT
10V/div 12V 1V/div
5V VOUT 1V/div 0V VDH 10V/div 0V 5V 5V/div 40s/div
IL
10A/div 0 10A/div VDL
IIN 1ms/div
0
PREBIASED STARTUP (OUTPUT PREBIASED AT 1.5V)
MAX8543 toc18
VIN
5V/div 2.5V
VOUT 1.5V VLX
500mV/div
10V/div
VDL 1ms/div
5V/div
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted.)
BODE PLOT, 600kHz, 15A LOAD
MAX8543 toc19
BODE PLOT, 600kHz, NO LOAD
MAX8543 toc20
SWEEP TIME 10.000s
SWEEP TIME 10.000s
0dB
90 30/div
0dB
90 30/div
10dB/div
10dB/div
1kHz
10kHz
100kHz
1MHz
1kHz
10kHz
100kHz
1MHz
Pin Description
PIN MAX8543 1 2 MAX8544 2 3 NAME GND SS FUNCTION Ground. Connect to the analog ground plane. Soft-Start. Connect a 0.1F to 1F ceramic capacitor from SS to GND. This capacitor sets the soft-start period during startup. See the Startup and Soft-Start section. SS is internally pulled to GND in shutdown. Compensation. Connect to an external RC network to compensate the feedback loop. See the Compensation Design section. COMP is internally pulled to GND in shutdown. Output Feedback. Connect to the center of a voltage-divider connected between OUT and GND to set the output voltage. The FB threshold voltage is 0.8V. Enable. Drive EN logic high to enable the output, or drive logic low for shutdown. Connect EN to IN for always-on operation. Negative Differential Current-Sensing Input Positive Differential Current-Sensing Input Digital Programmable Current-Limit Input for Inductor Current Sensing (VCS+ - VCS-). See Table 3. Power Ground. Connect to the power ground plane and to the source of the low-side external MOSFETs. Connect PGND to GND at a single point. Low-Side MOSFET Gate-Driver Output. Connect to the gate of the low-side external MOSFETs. DL is pulled low in shutdown. Internal 5V Linear-Regulator Output. Connect a 1F to 10F ceramic capacitor from VL to PGND. Connect VL to IN for VIN less than 5.5V. VL provides power for bias and gate drive. Input Supply Voltage. IN is the input to the internal linear regulator. Connect VL to IN for VIN less than 5.5V.
3 4 5 6 7 -- 8 9 10
4 5 6 7 8 9 -- 12 13
COMP FB EN CSCS+ ILIM1 ILIM PGND DL
11
14
VL
12
15
IN
10
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP
Pin Description (continued)
PIN MAX8543 13 14 15 MAX8544 16 17 18 NAME LX DH BST Inductor Connection High-Side MOSFET Gate-Driver Output. Connect DH to the gate of the high-side external MOSFETs. DH is pulled low in shutdown. Boost Capacitor Connection. Connect a 0.1F or larger ceramic capacitor from BST to LX. BST provides power for the high-side MOSFET gate drive. Frequency Set and Synchronization. Connect a resistor from FSYNC to GND to set the switching frequency or drive with a clock signal to synchronize between 160kHz and 1.2MHz. See the Switching Frequency and Synchronization section. Analog Programmable Current-Limit Input for Low-Side MOSFET (VLX - VPGND). Connect a resistor from ILIM2 to ground to set the overcurrent threshold. See the Setting the Current Limits section. Current-Limit Operating-Mode Selection. Connect MODE to VL for latch-off current limit or connect to GND for automatic-recovery current limit with the MAX8544. The MAX8543 always uses automatic-recovery current limit. Power-OK. POK is an open-drain output that is high impedance when the output is above 91% of its nominal regulation voltage. POK is pulled low when the output is out of regulation and when the part is in shutdown. To use POK as a logic-level signal, connect a pullup resistor from POK to the logic supply. Synchronization Output. Provides a clock output that is 180 out of phase with the rising edge of DH for out-of-phase synchronization of another MAX8544. FUNCTION
MAX8543/MAX8544
16
19
FSYNC
--
1
ILIM2
--
10
MODE
--
11
POK
--
20
SYNCO
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
VIN = (10.8V TO 13.2V) C12 9 SYNC IN D2 ON OFF R6 19 6 2 C5 3 C7 C8 SS ILIM1 IN 15 D1 FSYNC EN DH GND BST 18 17 C3 VOUT = 2.5V UP TO 15A C6A C9 C6B N1 N2 C4A C4B C4C VL C1
MAX8544EEP
LX VL DL
16 14 13 VL C2 N4 N3 R4
L1
R3
4
COMP PGND 12 R5 8 7 20 C11 C10
R2
5 10
FB CS+ MODE CSSYNCO
R8 VL
1
ILIM2
SYNC OUT
R9
R1 11 POK
POK R7
Figure 1. Typical Applications Circuit with 12V (10%) Input, 2.5V Output at Up to 15A, and 600kHz Switching Frequency
12
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
Table 1. Suggested Components for Figure 1
DESIGNATION C1 C2 C3 C4A, C4B, C4C C5 C6A, C6B C7 C8 C9, C10 C11 C12 D1 D2 L1 N1, N2 N3, N4 R1 R2 R3 R4, R5 R6 R7 R8 R9 QTY 1 1 1 2 1 2 1 1 2 1 1 1 1 1 2 2 1 1 1 2 1 1 1 1 DESCRIPTION 1F 20%, 16V X5R ceramic capacitor (0603) Panasonic ECJ1VB1C105M or equivalent 10F 20%, 6.3V X5R ceramic capacitor (0805) Panasonic ECJ2FB0J106M or Taiyo Yuden JMK212BJ106MG 0.1F 10%, 50V X7R ceramic capacitor (0603) TDK C1608X7R1H104KT or equivalent 10F 20%, 16V X5R ceramic capacitors (1206) Panasonic ECJ3YB1C106M or equivalent 0.22F 10%, 10V X7R ceramic capacitor (0603) Taiyo Yuden LMK107BJ224KA or equivalent 180F, 4V aluminum poly SPCAPs Panasonic EEFUE0G181XR 10pF, 50V C0G ceramic capacitor (0603) 220pF 10%, 50V X7R ceramic capacitor (0603) 0.47F 10% X7R ceramic capacitors (0603) 100pF, 50V C0G ceramic capacitor (0603) 470F 20%, 16V aluminum electrolytic capacitor Rubycon 16MBZ470M 100mA, 30V Schottky diode (SOT-323) Central CMSSH-3 250mA, 100V switching diode (SOT23) Central CMPD914 0.82H, 33A, 1.6m inductor Vishay IHLP-5050FD-01 0.82H N-channel MOSFETs IRF IRF7821 N-channel MOSFETs IRF IRF7832 17.4k 1% resistor (0603) 8.06k 1% resistor (0603) 220k 5% resistor (0603) 1.3k 5% resistors (0603) 42.2k 1% resistor (0603) 90.9k 1% resistor (0603) 9.31k 1% resistor (0603) 100k 5% resistor (0603)
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
VIN = (3V TO 3.6V) C12 8 SYNC IN D2 ON OFF 5 1 C5 2 C7 C8 SS R6 16 ILIM IN C1 12 D1 FSYNC EN BST DH 15 14 C3 VOUT = 2.5V UP TO 15A C6A C9 C6B N1 N2 C4A C4B C4C C4D
MAX8543
GND
LX 11 VL C2 DL 10
13 IN N3 N4 R4
L1
R3
3
COMP PGND 9
R2
4 6 R1
FB CS+ CS-
7 C10 R5
C11
Figure 2. Typical Applications Circuit with 3.3V (10%) Input, 2.5V Output at Up to 15A, and 500kHz Switching Frequency
14
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
Table 2. Suggested Components for Figure 2
DESIGNATION C1 C2 C3 C4A, C4B, C4C, C4D C5 C6A, C6B C7 C8 C9, C10 C11 C12 D1 D2 L1 N1, N2 N3, N4 R1 R2 R3 R4, R5 R6 QTY 1 1 1 4 1 2 1 1 2 1 1 1 1 1 2 2 1 1 1 2 1 DESCRIPTION 1F 10%, 16V X5R ceramic capacitor (0603) Panasonic ECJ1VB1C105K or equivalent 10F 20%, 6.3V X5R ceramic capacitor (0805) Panasonic ECJ2FB0J106M or Taiyo Yuden JMK212BJ106MG 0.1F 10%, 50V X7R ceramic capacitor (0603) TDK C1608X7R1H104KT or equivalent 10F 20%, 16V X5R ceramic capacitors (1206) Panasonic ECJ3YB1C106M or equivalent 0.22F 10%, 10V X7R ceramic capacitor (0603) Taiyo Yuden LMK107BJ224KA or equivalent 180F, 4V, 10m aluminum poly SPCAPs Panasonic EEFUE0G181XR 12pF, 50V C0G ceramic capacitor (0603) 220pF 10%, 50V X7R ceramic capacitor (0603) 0.47F 10% X7R ceramic capacitors (0603) 100pF, 50V C0G ceramic capacitor (0603) 470F 20%, 6.3V POSCAP Sanyo 6PB470M 100mA, 30V Schottky diode (SOT-323) Central CMSSH-3 250mA, 100V switching diode (SOT23) Central CMPD914 0.33H, 16A, 2m inductor (13 x 10 x 6.35) Coilcraft DO3316P-331HC N-channel MOSFETs Vishay Si4866DY N-channel MOSFETs Vishay Si4866DY 17.4k 1% resistor (0603) 8.06k 1% resistor (0603) 150k 5% resistor (0603) 680 5% resistors (0603) 53.6k 1% resistor (0603)
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15
Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
Detailed Description
DC-DC Converter Control Architecture
The MAX8543/MAX8544 step-down controllers use a PWM, current-mode control scheme. An internal transconductance amplifier establishes an integrated error voltage. The heart of the PWM controller is an open-loop comparator that compares the integrated voltage-feedback signal against the amplified currentsense signal plus the slope-compensation ramp, which are summed into the main PWM comparator to preserve inner-loop stability and eliminate inductor staircasing. At each rising edge of the internal clock, the high-side MOSFET turns on until the PWM comparator trips or the maximum duty cycle is reached or the peak current limit is reached. During this on-time, current ramps up through the inductor, storing energy in a magnetic field and sourcing current to the output. The current-mode feedback system regulates the peak inductor current as a function of the output-voltageerror signal. The circuit acts as a switch-mode transconductance amplifier and pushes the output LC filter pole normally found in a voltage-mode PWM to a higher frequency. During the second half of the cycle, the high-side MOSFET turns off and the low-side MOSFET turns on. The inductor releases the stored energy as the current ramps down, providing current to the output. The output capacitor stores charge when the inductor current exceeds the required load current and discharges when the inductor current is lower, smoothing the voltage across the load. Under soft-overload conditions, when the peak inductor current exceeds the selected current limit (see the Current-Limit Circuit section), the high-side MOSFET is turned off immediately and the low-side MOSFET is turned on and remains on to let the inductor current ramp down until the next clock cycle. Under heavy-overload or short-circuit conditions, the valley foldback current limit is enabled to reduce power dissipation of external components. The MAX8543/MAX8544 operate in a forced-PWM mode. As a result, the controller maintains a constant switching frequency, regardless of load, to allow for easier filtering of the switching noise.
Undervoltage Lockout
When VL drops below 2.62V, the MAX8543/MAX8544 assume that the supply voltage is too low for proper operation, so the undervoltage-lockout (UVLO) circuitry inhibits switching and forces the DL and DH gate drivers low. When VL rises above 2.7V, the controller enters the startup sequence and then resumes normal operation.
Startup and Soft-Start
The soft-start circuitry gradually ramps up the reference voltage to control the rate of rise of the step-down controller output and reduce input surge currents during startup. The soft-start period is determined by the value of the capacitor from SS to GND. The soft-start time is approximately (33ms/F) x CSS. The MAX8543/MAX8544 also feature prebias startup; therefore, both external power MOSFETs are kept off if the voltage at FB is higher than that at SS. This allows the MAX8543/MAX8544 to start up into a prebiased output without pulling the output voltage down. Before the MAX8543/MAX8544 can begin the soft-start and power-up sequence, the following conditions must be met: 1) VVL exceeds the 2.7V undervoltage-lockout threshold. 2) EN is at logic high. 3) The thermal limit is not exceeded.
Enable
The MAX8543/MAX8544 feature a low-power shutdown mode. A logic low at EN shuts down the controller. During shutdown, the output is high impedance, and both DH and DL are low. Shutdown reduces the quiescent current (IQ) to less than 10A. A logic high at EN enables the controller.
Synchronous-Rectifier Driver (DL)
Synchronous rectification reduces conduction losses in the rectifier by replacing the normal Schottky catch diode with a low-resistance MOSFET switch. The MAX8543/MAX8544 also use the synchronous rectifier to ensure proper startup of the boost gate-driver circuit and to provide the current-limit signal. The DL low-side gate-drive waveform is always the complement of the DH high-side gate-drive waveform (with controlled dead time to prevent cross-conduction or shootthrough). An adaptive dead-time circuit monitors the DL voltage and prevents the high-side MOSFET from turning on until DL is fully off. For the dead-time circuit to work properly, there must be a low-resistance, lowinductance path from the DL driver to the MOSFET gate. Otherwise, the sense circuitry in the MAX8543/ MAX8544 can interpret the MOSFET gate as off when gate charge actually remains.
Internal 5V Linear Regulator (VL)
All MAX8543/MAX8544 functions are powered from the on-chip, low-dropout, 5V linear regulator. Connect a 1F to 10F ceramic capacitor from VL to PGND. In applications where the input voltage is less than 5.5V, bypass the linear regulator by connecting VL to IN.
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP
Use very short, wide traces, about 10 to 20 squares (50 mils to 100 mils wide if the MOSFET is 1in from the device) for the gate drive. The dead time at the other edge (DH turning off) also has an adaptive dead-time circuit operating in a similar manner. For both edges, there is an additional fixed dead time after the adaptive dead time expires.
Current-Limit Circuit
The MAX8543/MAX8544 use both valley foldback current limiting and peak constant current limiting, simultaneously (Figure 4). The valley foldback current limit is used to reduce power dissipation of external components, mainly inductor and power MOSFETs, and upstream power source, when output is severely overloaded or short circuited. Thus the circuit can withstand short-circuit conditions indefinitely without causing overheating of any component. The peak constant current limit sets the current-limit point more accurately since it does not have to suffer the wide variation of the low-side power MOSFET's on-resistance due to tolerance and temperature. The valley current is sensed across the on-resistance of the low-side MOSFET (VPGND - VLX). The valley current limit trips when the sensed current exceeds the valley current-limit threshold. The valley current limit recovers when the sensed current drops below the valley currentlimit threshold (except when using the latch-off option with the MAX8544). Set the minimum valley current-limit threshold, when the output voltage is at a nominal regulated value, higher than the maximum peak current-limit setting. With this method, the current-limit point accuracy is controlled by the peak current limit and is not interfered with by the wide variation of MOSFET on-resistance. See the Setting the Current Limits section for how to set these limits. The MAX8543 has a fixed valley current-limit threshold and fixed foldback ratio. The MAX8544 can select between an adjustable valley current-limit threshold with adjustable foldback ratio and a fixed valley current limit without foldback for latch-off. When latch-off is used (MODE is connected to VL), set the current-limit threshold by only one resistor from ILIM2 to GND and make sure this threshold is higher than the maximum output current required by at least a 20% margin. Cycle EN or input power to reset the current-limit latch. The peak current limit is used to sense the inductor current, and is more accurate than the valley current limit since it does not depend upon the on-resistance of the low-side MOSFET. The peak current can be measured across the resistance of the inductor for the highest efficiency, or alternatively, a current-sense resistor can be used for more accurate current sensing. The MAX8543/MAX8544 have four selectable peak currentlimit thresholds that are selected using ILIM (MAX8543) or ILIM1 (MAX8544). See Table 3 for the current-limit settings. For more information on the current limit, see the Setting the Current Limits section.
MAX8543/MAX8544
High-Side Gate-Drive Supply (BST)
A flying capacitor boost circuit (Figure 3) generates the gate-drive voltage for the high-side n-channel MOSFET. The capacitor between BST and LX is charged from VL up to VVL minus the diode forward-voltage drop while the low-side MOSFET is on. When the low-side MOSFET is switched off, the stored voltage of the capacitor is stacked above LX to provide the necessary turn-on voltage (VGS) for the high-side MOSFET. The controller then closes an internal switch between BST and DH to turn the high-side MOSFET on.
Current-Sense Amplifier
The MAX8543/MAX8544 current-sense circuit amplifies the differential current-sense voltage (VCS+ - VCS-). The gain of the current-sense amplifier is determined by the states of ILIM and ILIM1. This amplified current-sense signal and the internal slope-compensation signal are summed (VSUM) together and fed into the PWM comparator's inverting input. The PWM comparator shuts off the high-side MOSFET when V SUM exceeds the integrated feedback voltage (VCOMP). The differential current sense is also used to provide peak inductor current limiting. This current limit is more accurate than the valley current limit, which is measured across the low-side MOSFET's on-resistance.
IN BST DH N
MAX8543/ MAX8544
LX DL N
Figure 3. The boost circuit provides voltage for the high-side MOSFET gate drive.
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
IPEAK
ILOAD INDUCTOR CURRENT
MAX8543/ MAX8544
LX
R1
IVALLEY
FB
R2
TIME
Figure 4. Inductor-Current Waveform
Figure 5. Setting the Output Voltage with a Resistor VoltageDivider
Switching Frequency and Synchronization
The MAX8543/MAX8544 have an adjustable internal oscillator that can be set to any frequency from 200kHz to 1MHz. To set the switching frequency, connect a resistor from FSYNC to GND. Calculate the resistor value from the following equation: 1 1k RFSYNC = - 240ns 2fS 14.18ns The MAX8543/MAX8544 can also be synchronized to an external clock by connecting the clock signal to FSYNC. When using an external clock, select RFSYNC such that the free-running frequency is within 30% of the clock frequency. In addition, the MAX8544 has a synchronization output (SYNCO) that provides a clock signal that is 180 out-of-phase with the MAX8544 switching. SYNCO is used to synchronize a second controller 180 out-ofphase with the first by connecting SYNCO of the first controller to FSYNC of the second when the first controller operates in free-running mode. When the first controller is synchronized to an external clock, the external clock is inverted to generate SYNCO.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX8543/MAX8544. When the junction temperature exceeds TJ = +160C, an internal thermal sensor shuts down the device, allowing the IC to cool. The thermal sensor turns the IC on again after the junction temperature cools by 15C, resulting in a pulsed output during continuous thermal-overload conditions.
Design Procedure
Setting the Output Voltage
To set the output voltage for the MAX8543/MAX8544, connect FB to the center of an external resistor-divider from the output to GND (Figure 5). Select R2 between 8k and 24k; then calculate R1 with the following equation: V R1 = R2 x OUT - 1 VFB where VFB = 0.8V. R1 and R2 should be placed as close to the IC as possible.
Inductor Selection
There are several parameters that must be examined when determining which inductor is to be used: input voltage, output voltage, load current, switching frequency, and LIR. LIR is the ratio of peak-to peak inductor current ripple to maximum DC load current. A higher LIR value allows for a smaller inductor, but results in higher losses and higher output ripple.
Power-Good Signal (POK)
POK is an open-drain output on the MAX8544 that monitors the output voltage. When the output is above 91% of its nominal regulation voltage, POK is high impedance. When the output drops below 91% of its nominal regulation voltage, POK is pulled low. POK is also pulled low when the MAX8544 is shut down. To use POK as a logiclevel signal, connect a pullup resistor from POK to the logic-supply rail.
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP
A good compromise between size and efficiency is an LIR of 0.3. Once all the parameters are chosen, the inductor value is determined as follows: L= VOUT x (VIN - VOUT ) VIN x fS x ILOAD(MAX) x LIR Ensure that ILIM is equal to or greater than the maximum load current at peak current limit (see the Peak Current Limit section): ISC = I 0.04 V + P -P 2 RDS(ON)
MAX8543/MAX8544
where fS is the switching frequency. Choose a standardvalue inductor close to the calculated value. The exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and efficiency. Lower inductor values minimize size and cost, but they also increase the output ripple and reduce the efficiency due to higher peak currents. On the other hand, higher inductor values increase efficiency, but eventually resistive losses due to extra turns of wire exceed the benefit gained from lower AC current levels. This is especially true if the inductance is increased without also increasing the physical size of the inductor. Find a low-loss inductor with the lowest possible DC resistance that fits the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 300kHz. The chosen inductor's saturation current rating must exceed the peak inductor current determined as: IPEAK = ILOAD(MAX) + LIR x ILOAD(MAX) 2
where 40mV is the maximum current-limit threshold when the output is shorted (VOUT = 0V). The MAX8544 has an adjustable valley current limit and can be selected for foldback with automatic recovery, or constant current with latch-up. To set the current limit for foldback mode, connect a resistor from ILIM2 to the output (R FOBK ), and another resistor from ILIM2 to GND (RILIM). See Figure 6. The values of RFOBK and RILIM are calculated as follows: 1) First, select the percentage of foldback (PFB). This percentage corresponds to the current limit when VOUT equals zero, divided by the current limit when VOUT equals a nominal voltage. A typical value of PFB is in the range of 15% to 40%. A lower value of PFB yields lower short-circuit current. The following equations are used to calculate RFOBK and RILIM: RFOBK = PFB x VOUT 5A x (1 - PFB )
Setting the Current Limits
Valley Current Limit The valley current limit employs a current foldback scheme. The MAX8543 has a fixed valley current-limit threshold of 130mV, and a fixed foldback ratio (PFB) of 23%. The foldback ratio is the current-limit threshold when the output is at 0V (output shorted to ground), divided by the threshold when the output is at its nominal regulated value. Thus, the minimum output current limit (ILIM) and maximum short-circuit current (ISC) is calculated as: ILIM = I 0.11V + P -P 2 RDS(ON)
RILIM =
5 x RDS(ON) x IVALLEY x (1 - PFB ) x RFOBK VOUT - 5 x RDS(ON) x IVALLEY x (1 - PFB )
[
]
where IVALLEY is the value of the inductor valley current at maximum load (ILOAD(MAX) - 1/2 IP-P), and RDS(ON) is the maximum on-resistance of the low-side MOSFET at the highest operating junction temperature.
MAX8544
LX
OUT
where RDS(ON) is the maximum on-resistance of the low-side MOSFET at the highest expected operating junction temperature, and IP-P is the inductor ripple current, calculated as: IP - P
RFOBK
ILIM2
RILIM
(VIN - VOUT ) x VOUT =
fS x L x VIN
Figure 6. ILIM2 Resistor Connections
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
2) If the resulting value of R ILIM is negative, either increase PFB or choose a low-side MOSFET with a lower RDS(ON). The latter is preferred as it increases the efficiency and results in a lower short-circuit current. To set the constant current limit for the latch-up mode, only RILIM is used. The equation for RILIM below sets the current-limit threshold at 1.2 times the maximumrated output current: RILIM = 1.2 x IVALLEY x RDS(ON) 1A To use the DC resistance of the output inductor for current sensing, an RC circuit is added (see Figure 7). The RC time constant is set to be twice the inductor (L / RDC) time constant. Pick the value of R4 in the range of 470 to 2k, and then calculate the capacitor value from: C9 = 2L / (RDC x R4). Add a resistor (R5) equal in value to R4 to the CS- connection to minimize input-offset error. The equivalent current-sense resistance is equal to the DC resistance of the inductor (RDC). To use a current-sense resistor, connect the resistor as shown in Figure 8. Since most current-sense resistors have inductance, the RC circuit is also required and is calculated in the same manner as inductor current sensing. Place C11 close to CS+ and CS- pins to decouple the high-frequency noise pickup. Place C10 (same value as C9) across R5 to aid in shortcircuit recovery.
Similarly, I VALLEY is the value of the inductor valley current at maximum load, RDS(ON) is the maximum onresistance of the low-side MOSFET at the highest operating junction temperature. Peak Current Limit Peak inductor current-limit threshold (VTH) has four possible settings through ILIM (MAX8543) or ILIM1 (MAX8544) as shown in Table 3 below. The resulting current limit is calculated as: ILIM = VTH IP - P - RDC 2
L1
VOUT
LX MAX8543/ MAX8544
R4 C9
where RDC is either the DC resistance of the inductor or the value of the optional current-sense resistor. Note that VILIM is a logic-level setting, and can allow a variation of 0.1 x VVL without affecting VTH. To ensure maximum output current, use the minimum value of VTH from each setting, and the maximum RDC values at the highest expected operating temperature. The DC resistance of the inductor's copper wire has a +0.22%/C temperature coefficient.
CS+
C11
R5
C10
CS-
Figure 7. Inductor RDC Current Sensing
Table 3. ILIM Current-Limit Threshold Settings
VILIM 0 GND RECOMMENDED ILIM CONNECTION VTH MIN (mV) 38.5 85.0 VTH TYP (mV) 50 100 VTH MAX (mV) 56.5 115.0
L1 R3 VOUT
LX MAX8543/ MAX8544
R4 C9
Voltage-divider: 1/3 VVL 100k from ILIM/ILIM1 to GND 200k from ILIM/ILIM1 to VL Voltage-divider: 2/3 VVL 200k from ILIM/ILIM1 to GND 100k from ILIM/ILIM1 to VL VVL VL
CS+
C11
R5
C10
CS-
127.5 170.0
150 200
172.5 230.0
Figure 8. Using a Current-Sense Resistor
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP
MOSFET Selection
The MAX8543/MAX8544 drive two or four external, logic-level, n-channel MOSFETs as the circuit switch elements. The key selection parameters are: 1) On-resistance (RDS(ON)): the lower, the better. 2) Maximum drain-to-source voltage (V DSS): should be at least 20% higher than the input supply rail at the high-side MOSFET's drain. 3) Gate charges (QG, QGD, QGS): the lower, the better. For a 3.3V input application, choose a MOSFET with a rated RDS(ON) at VGS = 2.5V. For a 5V input application, choose the MOSFETs with rated RDS(ON) at VGS 4.5V. For a good compromise between efficiency and cost, choose the high-side MOSFET (N1, N2) that has conduction losses equal to the switching loss at nominal input voltage and output current. The selected low-side MOSFET (N3, N4) must have an RDS(ON) that satisfies the current-limit-setting condition above. Ensure that the lowside MOSFET does not spuriously turn on due to dV/dt caused by the high-side MOSFET turning on as this would result in shoot-through current and degrade the efficiency. MOSFETs with a lower QGD / QGS ratio have higher immunity to dV/dt. For high-current applications, it is often preferable to parallel two MOSFETs rather than to use a single large MOSFET. For proper thermal-management design, the power dissipation must be calculated at the desired maximum operating junction temperature, maximum output current, and worst-case input voltage (for the low-side MOSFET, worst case is at VIN(MAX); for the high-side MOSFET, it could be either at VIN(MAX) or VIN(MIN)). The high-side and low-side MOSFETs have different loss components due to the circuit operation. The low-side MOSFET operates as a zero-voltage switch; therefore, major losses are the channel-conduction loss (PLSCC) and the bodydiode conduction loss (PLSDC): V PLSCC = 1 - OUT x I2 x RDS(ON) LOAD VIN Use RDS(ON) at TJ(MAX): PLSDC = 2 x ILOAD x VF x t DT x fS where VF is the body-diode forward-voltage drop, tDT is the dead time between high-side and low-side switching transitions, and fS is the switching frequency. The high-side MOSFET operates as a duty-cycle control switch and has the following major losses: the channelconduction loss (PHSCC), the VI overlapping switching loss (PHSSW), and the drive loss (PHSDR). The high-side MOSFET does not have body-diode conduction loss because the diode never conducts current: V PHSCC = OUT x I2 x RDS(ON) LOAD VIN Use RDS(ON) at TJ(MAX): PHSSW = VIN x ILOAD x QGS + QGD x fS IGATE
MAX8543/MAX8544
where IGATE is the average DH-driver output current capability determined by: IGATE 0.5 x VVL RDS(ON)(HS) + RGATE
where RDS(ON)(HS) is the high-side MOSFET driver's on-resistance (1, typ) and RGATE is the internal gate resistance of the MOSFET (0.5 to 3): PHSDR = QG x VGS x fS x where VGS VVL. In addition to the losses above, allow about 20% more for additional losses due to MOSFET output capacitances and low-side MOSFET body-diode reverse-recovery charge dissipated in the high-side MOSFET, but it is not well defined in the MOSFET data sheet. Refer to the MOSFET data sheet for thermal resistance specifications to calculate the PC board area needed to maintain the desired maximum operating junction temperature with the above calculated power dissipations. To reduce EMI caused by switching noise, add a 0.1F ceramic capacitor from the high-side switch drain to the low-side switch source or add resistors in series with DH and DL to slow down the switching transitions. However, adding series resistors increases the power dissipation of the MOSFET, so be sure this does not overheat the MOSFET. RGATE RGATE + RDS(ON)(HS)
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
MOSFET Snubber Circuit
Fast switching transitions cause ringing because of resonating circuit parasitic inductance and capacitance at the switching nodes. This high-frequency ringing occurs at LX's rising and falling transitions and can interfere with circuit performance and generate EMI. To dampen this ringing, a series RC snubber circuit is added across each switch. Below is the procedure for selecting the value of the series RC circuit. Connect a scope probe to measure VLX to GND and observe the ringing frequency, fR. Find the capacitor value (connected from LX to GND) that reduces the ringing frequency by half. The circuit parasitic capacitance (CPAR) at LX is then equal to 1/3rd the value of the added capacitance above. The circuit parasitic inductance (LPAR) is calculated by: LPAR = 1 IRMS has a maximum value when the input voltage equals twice the output voltage (VIN = 2 x VOUT), so IRMS(MAX) = ILOAD / 2. Ceramic capacitors are recommended due to their low ESR and ESL at high frequency with relatively low cost. Choose a capacitor that exhibits less than 10C temperature rise at the maximum operating RMS current for optimum long-term reliability. Ceramic capacitors with an X5R or better temperature characteristic are recommended. When operating from a soft input source, an additional input capacitor (bulk bypass capacitor) may be required to prevent input from sagging.
Output Capacitor
The key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (ESR), the equivalent series inductance (ESL), and the voltage-rating requirements. These parameters affect the overall stability, output voltage ripple, and transient response. The output ripple has three components: variations in the charge stored in the output capacitor, the voltage drop across the capacitor's ESR, and ESL caused by the current into and out of the capacitor. The maximum output voltage ripple is estimated as follows: VRIPPLE = VRIPPLE(ESR) + VRIPPLE(C) + VRIPPLE(ESL) The output voltage ripple as a consequence of the ESR, ESL, and output capacitance is: VRIPPLE(ESR) = IP - P x ESR V VRIPPLE(ESL) = IN x ESL L VRIPPLE(C) = IP - P 8 x COUT x fS
(2fR )
2
x CPAR
The resistor for critical dampening (RSNUB) is equal to 2 x fR x LPAR. Adjust the resistor value up or down to tailor the desired damping and the peak voltage excursion. The capacitor (CSNUB) should be at least 2 to 4 times the value of the CPAR to be effective. The power loss of the snubber circuit (PRSNUB) is dissipated in the resistor and can be calculated as: PRSNUB = CSNUB x ( VIN ) x fSW
2
where VIN is the input voltage and fSW is the switching frequency. Choose an RSNUB power rating that meets the specific application's derating rule for the power dissipation calculated.
Input Capacitor
The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit's switching. The input capacitor must meet the ripple-current requirement (IRMS) imposed by the switching currents defined by the following equation: IRMS = ILOAD VOUT x ( VIN - VOUT ) VIN
where IP-P is the peak-to-peak inductor current: V - VOUT VOUT IP - P = IN x fS x L VIN These equations are suitable for initial capacitor selection, but final values should be chosen based on a prototype or evaluation circuit. As a general rule, a smaller current ripple results in less output voltage ripple. Since the inductor ripple current is a factor of the inductor value and input voltage, the output voltage ripple decreases with larger inductance, and increases with higher input voltages. Polymer, tantalum, or aluminum electrolytic capacitors are recommended.
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP
The aluminum electrolytic capacitor is the least expensive; however, it has higher ESR. To compensate for this, use a ceramic capacitor in parallel to reduce the switching ripple and noise. For reliable and safe operation, ensure that the capacitor's voltage and ripple-current ratings exceed the calculated values. The response to a load transient depends on the selected output capacitors. After a load transient, the output voltage instantly changes by ESR x I LOAD. Before the controller can respond, the output voltage deviates further depending on the inductor and output capacitor values. After a short period of time (see the Typical Operating Characteristics), the controller responds by regulating the output voltage back to its nominal state. The controller response time depends on its closed-loop bandwidth. With a higher bandwidth, the response time is faster, thus preventing the output voltage from further deviation from its regulation value. The basic regulator loop is modeled as a power modulator, output feedback divider, and an error amplifier. The power modulator has DC gain set by gmc x RLOAD, with a pole and zero pair set by R LOAD, the output capacitor (COUT), and its ESR. Below are equations that define the power modulator: GMOD(dc) = gmc x RLOAD x fS x L RLOAD + (fS x L)
MAX8543/MAX8544
where RLOAD = VOUT / IOUT(MAX), fS is the switching frequency, L is the output inductance, and g mc = 1 / (AVCS x RDC), where AVCS is the gain of the current-sense amplifier and RDC is the DC resistance of the inductor (or current-sense resistor). A VCS is dependent on the current-limit selection at ILIM, and ranges from 3 to 11 (see Current-Sense Amplifier Voltage Gain in the Electrical Characteristics table). The frequencies at which the pole and zero created by the power modulator are determined as follows: fpMOD = 1 RLOAD x fS x L 2 x COUT x + ESR RLOAD + (fS x L) fzMOD = 1 2 x COUT x ESR
Compensation Design
The MAX8543/MAX8544 use an internal transconductance error amplifier whose output compensates the control loop. The external inductor, output capacitor, compensation resistor, and compensation capacitors determine the loop stability. The inductor and output capacitor are chosen based on performance, size, and cost. Additionally, the compensation resistor and capacitors are selected to optimize control-loop stability. The component values, shown in the Typical Application Circuits (Figures 1 and 2), yield stable operation over the given range of input-to-output voltages. The controller uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor, so the MAX8543/ MAX8544 use the voltage drop across the DC resistance of the inductor or the alternate series current-sense resistor to measure the inductor current. Current-mode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor resulting in a smaller phase shift and requiring a less elaborate error-amplifier compensation than voltage-mode control. A simple single series RC and CC is all that is needed to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering. For other types of capacitors, due to the higher capacitance and ESR, the frequency of the zero created by the capacitance and ESR is lower than the desired closed-loop crossover frequency. To stabilize a nonceramic output-capacitor loop, add another compensation capacitor (CF) from COMP to GND to cancel this ESR zero.
When COUT is composed of "n" identical capacitors in parallel, the resulting COUT = n x COUT(EACH), and ESR = ESR(EACH) / n. Note that the capacitor zero for a parallel combination of like capacitors is the same as for an individual capacitor. The feedback voltage-divider has a gain of GFB = VFB / VOUT, where VFB is equal to 0.8V. The transconductance error amplifier has a DC gain, GEA(DC) = gmEA x RO, where gmEA is the error-amplifier transconductance, which is equal to 110S, RO is the output resistance of the error amplifier, which is 10M. A dominant pole is set by the compensation capacitor (CC), the amplifier output resistance (RO), and a zero is set by the compensation resistor (RC) and the compensation capacitor (CC). There is an optional pole set by CF and RC to cancel the output-capacitor ESR zero if it occurs near the crossover frequency (fC). Thus: fpdEA = 1 2 x CC x (RO + RC )
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23
Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
fzEA = 1 2 x CC x RC 1 2 x CF x RC For the case where fzMOD is less than fC: The power-modulator gain at fC is: GMOD( fc) = GMOD(dc) x The error-amplifier gain at fC is: f GEA ( fc) = gmEA x RC x zMOD fC RC is calculated as: V fC RC = OUT x VFB gmEA x GMOD( fc) x fzMOD where gmEA = 110S. CC is calculated from: R x f x L x COUT CC = LOAD S (RLOAD + (fS x L)) x RC CF is calculated from: GEA ( fc) = gmEA x RC fpMOD fC CF = 1 2 x RC x fzMOD fpMOD fzMOD
fpEA =
The crossover frequency, fC, should be much higher than the power-modulator pole fPMOD. Also, fC should be less than or equal to 1/5th the switching frequency. Select a value for fC in the range: f fpMOD << fC S 5 At the crossover frequency, the total loop gain must equal 1, and is expressed as: GEA ( fc) x GMOD( fc) x VFB =1 VOUT
For the case where fzMOD is greater than fC:
GMOD( fc) = GMOD(dc) x then RC can be calculated as: RC =
VOUT gmEA x VFB x GMOD( fc)
Below is a numerical example to calculate RC and CC values of the typical operating circuit of Figure 1 (MAX8544): AVCS = 11 (for ILIM1 = GND) RDC = 2.5m gmc = 1 / (AVCS x RDC) = 1 / (11 x 0.0025) = 36.7S VOUT = 2.5V IOUT(MAX) = 15A RLOAD = VOUT / IOUT(MAX) = 2.5 / 15 = 0.167 COUT = 360F ESR = 5m
GMOD(dc) = gmc x = 36.36 RLOAD x fS x L RLOAD + (fS x L)
where gmEA = 110S. The error-amplifier compensation zero formed by RC and CC should be set at the modulator pole fPMOD. CC is calculated by: R x f x L x COUT CC = LOAD S (RLOAD + (fS x L)) x RC If fzMOD is less than 5 x fC, add a second capacitor CF from COMP to GND. The value of CF is calculated as follows: 1 CF = 2 x RC x fzMOD As the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same.
24
( ) = 4.50 0.167 + (600 x 10 ) x (0.8 x 10 )
0.167 x (600 x 103 ) x 0.8 x 10-6
3 -6
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP
Applications Information
fpMOD = 1 R xf xL 2 x COUT x LOAD S + ESR RLOAD + fS x L 1 = 3.43kHz 0.167 x (600 x 103 ) x 0.8 x 10 -6 -6 2 x (360 x 10 ) x + 0.005 0.167 + (600 x 103 ) x 0.8 x 10 -6
MAX8543/MAX8544
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. Follow these guidelines for good PC board layout: 1) Place IC decoupling capacitors as close to IC pins as possible. Keep separate the power ground plane and the signal ground plane. Place the input ceramic decoupling capacitor directly across and as close as possible to the high-side MOSFET's drain and the low-side MOSFET's source. This is to help contain the high switching current within this small loop. 2) For output current greater than 10A, a four-layer PC board is recommended. Pour a signal ground plane in the second layer underneath the IC to minimize noise coupling. 3) Connect input, output, snubber, and VL capacitors to the power ground plane; connect all other capacitors to the signal ground plane. 4) Place the inductor current-sense resistor and capacitor as close to the inductor as possible. Make a Kelvin connection to minimize the effect of PC board trace resistance. Place the input bias balance resistor and bypass capacitor (R5 and C10 in Figures 7 and 8) near CS-. Run two closely parallel traces from across the capacitor (C9 in Figures 7 and 8) to CS+ and CS-. Place the decoupling capacitor C11 close to CS+ and CS- pins. 5) Place the MOSFET as close as possible to the IC to minimize trace inductance of the gate-drive loop. If parallel MOSFETs are used, keep the trace lengths to both gates equal. 6) Connect the drain leads of the power MOSFET to a large copper area to help cool the device. Refer to the power MOSFET data sheet for recommended copper area. 7) Place the feedback and compensation components as close to the IC pins as possible. Connect the feedback-divider resistor from FB to the output as close as possible to the farthest output capacitor. Refer to the MAX8544 evaluation kit for an example layout.
=
f fpMOD << fC S 5 3.43kHz << fC < 120kHz; select fC = 120kHz. fzMOD = = 1 2 x COUT x ESR 1 2 x (360 x 10 -6 ) x 0.005
= 88.4kHz
Since fzMOD < fC:
GMOD( fc) = GMOD(dc) x = 4.5 x
fpMOD fzMOD = 0.175
3.43 x 103 88.4 x 103
V fC RC = OUT x VFB gmEA x GMOD( fc) x fzMOD =
CC = =
2.5 120 x 103 x = 220k 0.8 (110 x 10 -6 ) x 0.175 x (88.4 x 103 )
RLOAD x fS x L x COUT (RLOAD + fS x L) x RC 0.167(600 x 103 )(0.8 x 10 -6 )(360 x 10 -6 ) = 202pF 0.167 + (600 x 103 )(0.8 x 10 -6 ) (220 x 103 )
Select the nearest standard value: CC = 220pF CF = = 1 2 x RC x fzMOD 1 2 x (220 x 103 ) x (88.4 x 103 )
= 8.2pF
Select the nearest standard value: CF = 10pF: R3 = RC = 220k C8 = CC = 220pF C7 = CF = 10pF
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25
Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP MAX8543/MAX8544
Table 4. Suggested Component Manufacturers
MANUFACTURER Central Semiconductor Coilcraft International Rectifier Kamaya Panasonic Sanyo Sumida Taiyo Yuden TDK Vishay/Siliconix COMPONENT Diodes Inductors MOSFETs Resistors Capacitors Capacitors Inductors Capacitors Capacitors MOSFETs WEBSITE www.centralsemi.com www.coilcraft.com www.irf.com www.kamaya.com www.panasonic.com www.sanyo.com www.sumida.com www.t-yuden.com www.component.tdk.com www.vishay.com PHONE 631-435-1110 800-322-2645 310-322-3331 260-489-1533 714-373-7366 619-661-6835 847-956-0666 408-573-4150 847-803-6100 402-564-3131
Pin Configurations
TOP VIEW
GND 1 SS 2 COMP 3 FB 4 EN 5 CS- 6 CS+ 7 ILIM 8 16 FSYNC 15 BST 14 DH
Chip Information
TRANSISTOR COUNT: 4185 PROCESS: BiCMOS
MAX8543
13 LX 12 IN 11 VL 10 DL 9 PGND
ILIM2 1 GND 2 SS 3 COMP 4 FB 5 EN 6 CS- 7 CS+ 8 ILIM1 9 MODE 10
20 SYNCO 19 FSYNC 18 BST 17 DH
MAX8544
16 LX 15 IN 14 VL 13 DL 12 PGND 11 POK
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Step-Down Controllers with Prebias Startup, Lossless Sensing, Synchronization, and OVP
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX8543/MAX8544
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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